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Synchronisation et distribution d'horloges dans les circuits complexes (SOC) – cours au Collège de France par François Anceau, prévu le 12 mars 2014
« Swimming pool »-like distributed architecture for clock generation in large many-core SoC C. Shan, F. Anceau, D. Galayko, E. Zianbetov, , ISCAS 2014, june, 2014, Melbourne
Complexity in heterogeneous systems on chip : design and analysis challenges, D. Galayko, E. Blokhina, E. Zianbetov, A. Dudka, F. Anceau, E. Colinet, A. Korniienko, J. Juillard, P. Basset, ISCAS 2014, june, 2014, Melbourne
Distributed clock generator for synchronous SoC using ADPLL network,E. Zianbetov, D. Galayko, F. Anceau, M. Javidan, C. Shan, O. Billoint, A. Korniienko, E. Colinet, G. Scorletti, J. M. Akré, J. Juillard, In Custom Integrated Circuits Conference (CICC), 2013 IEEE (pp. 1-4). IEEE.
FPGA Prototyping of Large Reconfigurable ADPLL Network for Distributed Clock Generation, C. Shan, E. Zianbetov, W. Yu, F. Anceau, O. Billoint, D. Galayko, ReConfig 2013 conference, 9-11 déc 2013, Mexico
On-chip clock error characterization for clock distribution system, C. Shan, D. Galayko, F. Anceau, IEEE Computer Sosciety Symposium on VLSI, 5-7 aug. 2013, Natal, Brazil
Design and Modeling of ADPLL with sliding-window for wide range frequency tracking, C. Shan, F. Anceau et D. Galayko, NEWCAS 2012 international conference, Montreal, Canada
A highly linear 1-2.5GHz 10 bits CMOS DCO for digital phase/frequency synthesis, E. Zianbetov, M. Terosiet, M. Javidan, F. Anceau, D. Galayko, E. Colinet, J. Juillard, NEWCAS 2012 international conference, Montreal, Canada.
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